1. Field of the Invention
The present invention relates to a driving circuit for a display panel, and in particular, to a power saving circuit for a liquid crystal display (LCD) panel and a plasma display panel (PDP).
2. Background of the Related Art
FIG. 1 is a cross-sectional view illustrating a pixel structure of a plasma display panel (PDP) according to the related art. As shown in FIG. 1, one pixel includes an upper plate 6 and a lower plate 7 that are aligned to face each other separated by a discharge space 8. In FIG. 1, the upper plate 6 forms a display screen panel, and the discharge space 8 is sealed up with a discharge excitation gas such as Nexe2x80x94Xe mixture gas or Hexe2x80x94Xe mixture gas. A scan electrode 1 and a sustain electrode 2 are positioned on the upper plate, facing each other, and a data electrode 3 (or address electrode) aligned orthogonal to the scan electrode 1 and the sustain electrode 2 is formed on the lower plate 7. A dielectric body (not shown) is spread on the data electrode 3. In addition, a barrier rib 4 for dividing each pixel is arranged on the data electrode, and a phosphor layer 5 is spread on the dielectric body covering the barrier rib 4 and the address electrode 3.
Accordingly, three grooves corresponding to red (R), green (G) and blue (B) and spread along the barrier rib 4 compose one pixel. The plasma gas reacts with the phosphor layer 5, and thus, the pixel generates lights of red, green and blue.
FIG. 3 illustrates a related art PDP driving circuit. As shown in FIG. 3, the related art PDP driving circuit includes a PDP 9, a scan drive IC 10, a data drive IC 11, a scan common pulse generator 12, a sustain pulse generator 13, a scan common energy recovering unit 14 and a sustain energy recovering unit 15.
Each pixel of the PDP 9 is operated and controlled by a voltage inputted to the scan electrode 1, the sustain electrode 2 and the data electrode 3. The pixels positioned on a line 1-480 selected by the scan electrode 1 receive an effective data through the data electrode 3. The data inputted through the data electrode 3 causes discharge to the scan electrode 1 and the sustain electrode 2. Selection of one line implies that the voltage is applied to the scan electrode 1. Such an operation is performed by the scan drive IC 10, the scan common pulse generator 12 and a common voltage generator (not shown).
The scan common pulse generator 12 outputs a common pulse signal of VH level (VH greater than VDD) according to control signals {circle around (3)}, {circle around (4)} and the scan drive IC 10 outputs a pulse signal of VDD level according to a control signal {circle around (2)}. Accordingly, an added value of the common pulse signal and the pulse signal, namely a scan pulse signal is inputted to the scan electrode 1, thereby selecting one scan electrode line.
When one scan electrode line is selected, the data drive IC 11 outputs the effective data (video data) to the pixels existing on the corresponding display line. That is, the data drive IC 11 applies the data pulse of VDD level to the address electrode 3 according to a pixel data {circle around (1)} provided by a memory (not shown), thereby writing the pixel data on the pixels of the selected line.
The above operation is sequentially performed during an address period of FIG. 4. When the write operation of the pixel data is finished in regard to the pixels on all of the scan lines 1-480, the respective pixels emit a light during a sustain period as shown in FIG. 4. In the sustain period, the scan common pulse generator 12 outputs a first discharge sustain pulse signal of VH level according to the control signals {circle around (3)}, {circle around (4)}, and the sustain pulse generator 13 outputs a second discharge sustain pulse signal of VH level according to control signals {circle around (5)}, {circle around (6)}, at a timing different relative to a timing of the first discharge sustain pulse signal.
Accordingly, during the sustain period, the first and second discharge sustain pulse signals are alternately applied to the scan electrode 1 and the sustain electrode 2. Thus, the PDP generates a light recognizable by human beings. Numbers of the first and second discharge sustain pulse signals applied to the scan electrode 1 and the sustain electrode 2 are discriminated for a gradation display as described below.
As described above, when the operation for one sub-frame is finished by sequentially carrying out the address period and the sustain period, the recorded data of the pixels must be all deleted for a next sub-frame. This period is a reset period as shown in FIG. 4.
Thus, in the PDP, the gradation is embodied in a digital method, which differs from a general cathode ray tube (CRT). That is, the CRT controls a degree of luminance by varying a strength of an electron beam injected to the respective pixels in an analog method, while the PDP controls the degree of luminance of the phosphor layer 5 by discriminating the numbers of the first and second discharge sustain pulse signals.
As shown in FIG. 2, to embody 256 gradation for a display, one field (16.7 ms), which is a time for outputting one frame on a display screen according to the NTSC standard, is divided into 8 sub-frames SF1xcx9cSF8. The above-described operation of the reset period, scan period and sustain period is performed on each sub-frame. As shown in FIG. 2, the sustain period is increased in the respective frames at a ratio of 2n(n=0, 7). In addition, a luminance number of each sub-frame is discriminated into 8 bits. For instance, in order to set the luminance of a specific pixel to be 112 level, the addressing is performed on the 4th, 5th and 6th sub-frames (24+25+26=112). So as to maximize the luminance, the addressing is carried out on the whole frame.
Accordingly, to drive the related art PDP, the scan pulse signal is first applied to the scan electrode 1, and the data pulse signal is applied to the data electrode 3 with an identical timing to perform the record discharge. Then, the discharge sustain pulse signal is alternately applied to the scan electrode 1 and the sustain electrode 2 to perform the sustain discharge to sustain the luminance.
As shown in FIGS. 3-4, the sustain discharge is performed by charging or discharging a capacitance unit (not shown) between the panel electrodes. It is conventionally known that most of the pixel luminance results from the sustain discharge. As a result, the consumption power of the PDP is considerably dependent upon the consumption power of the sustain period. When a large-sized panel is driven, the consumption power of the entire PDP is increased because of the increase of the capacitance and the driving power between the panel electrodes. Therefore, various methods have been suggested for reducing power consumption during the sustain discharge, such as recovering an ineffective power lost by the discharge during the sustain period and recycling it during the charge.
As shown in FIG. 3, the related art operation for recovering and recycling the power consumed during the sustain period is performed by the scan common energy recovering unit 14 and the sustain energy recovering unit 15. The scan common energy recovering unit 14 is connected to an output node of the scan common pulse generator 12, and the sustain energy recovering unit 15 is connected to an output node of the sustain pulse generator 13. The constitution and operation of the scan common energy recovering unit 14 and the sustain energy recovering unit 15 are identical. The operation of the scan common energy recovering unit 14 will now be described.
FIGS. 5A and 5B respectively illustrate paths of the scan common energy recovering unit 14 for recovering and recycling the scan common pulse PSC outputted from the scan common pulse generator 12 during the sustain period. FIG. 6 illustrates waveforms of control signals for controlling the energy recovering and recycling operations of the scan common pulse generator 12.
As illustrated in FIG. 6, a control signal {circle around (7)} is enabled just before the scan common pulse PSC outputted from the scan pulse generator 12 transitions from a high level to a low level, in order to turn on a MOS device M1. Accordingly, the scan common pulse PSC is stored in a storage capacitor Cs through a coil, a diode D1 and the MOS device M1. Thus, the scan common energy recovering unit 14 recovers the energy consumed during the sustain period.
To recycle the energy stored in the storage capacitor Cs, a control signal {circle around (8)} is enabled before the scan common pulse PSC is generated, which turns on a MOS device M2 of the scan common energy recovering unit 14. As a result, the energy stored in the storage capacitor Cs is outputted to the output node of the scan common pulse generator 12 through a diode D2, the MOS device M2 and the coil, and recycled when the scan common pulse generator 12 is operated. That is, the output node of the scan common pulse generator 12 is driven to a voltage level stored in the storage capacitor Cs of the scan common energy recovery unit 14, which reduces the power consumption by the scan common pulse generator 12.
As described above, the related art display driving circuit and energy recovery circuit and methods thereof have various disadvantages. The related art PDP driving circuit can only recover the energy only during the sustain period. An energy recovering and recycling method in other address periods has not been suggested. Accordingly, energy efficiency is low.
A power saving circuit for reducing power required to drive columns of a liquid crystal display (LCD) has been disclosed in the U.S. Pat. No. 5,528,256 (See for example FIG. 4 of U.S. Pat. No. 5,528,256). The conventional power saving circuit for the LCD panel shorts each column line to a storage capacitor through a multiplexer, and stores a voltage of each column in the storage capacitor. Thereafter, electric charges stored before a row drive period are re-applied to one column line, and thus a voltage of the column line has an intermediate value (0V). The intermediate value is driven to a high level (6V) or low level (xe2x88x926V) in a next row drive period.
Accordingly, the conventional power saving circuit does not full-swing the voltage of the column from +6V to xe2x88x926V, but charges the voltage from 0V to xe2x88x926V and from 0V to +6V. Thus, a driving power of each column for the corresponding row drive period in a predetermined display cycle is reduced. The active matrix LCD display U.S. Pat. No. 5,528,256 (i.e. FIGS. 1-2) including column and row driver circuitry is shown in FIGS. 10-11.
As described above, however, the conventional power saving circuit for the LCD has various disadvantages. In the conventional LCD power saving circuit, when one column line has a voltage value below an average, a voltage of another column line is not stored in the storage capacitor, but moves to the column line having the voltage value below the average, which deteriorates energy recovery efficiency. In addition, the conventional power saving circuit includes the multiplexers for each column line, which is disadvantageous for integration.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a reduced power display, circuit for driving the same, and methods for operating a display and a driving circuit that substantially obviates one or more problems caused by disadvantages of the related art.
Another object of the present invention is to provide a power saving circuit of a display panel and method for operating same that increases integration.
Another object of the present invention is to provide a power saving circuit of a display panel and method for operating same that increases energy efficiency.
Another object of the present invention is to provide a power saving circuit of a display panel and method for operating same that selectively recovers energy during display of data.
Another object of the present invention is to provide a power saving circuit of a display panel and method for operating same that can be adapted to a low power display power.
Another object of the present invention is to provide a power saving circuit for a display panel that can be advantageous for integration and appropriate for embodiment in a low power display panel.
Another object of the present invention to provide a power saving circuit for a display panel that can improve energy efficiency by selectively recovering energy and performing a selective driving by an effective data.
To achieve at least the above-described objects in a whole or in part and in accordance with the present invention, there is provided a power saving circuit for a display panel that includes a display panel, a power switch that switches a power supply voltage, a drive IC that drives the display panel, and an energy recovering unit connected to the power switch and the drive IC to recover electric charges charged in a panel capacitor of the display panel through a first path of the drive IC and to provide the electric charges to the display panel through a second path of the drive IC when re-driving the display panel.
To further achieve the above objects in a whole or in part, there is provided a power saving circuit for a display panel in accordance with the present invention that includes a display panel, a power switch that switches a power supply voltage, a drive IC that drives the display panel, and an energy recovering unit connected to the power switch and the drive IC that recovers electric charges charged in a panel capacitor of the display panel through a first path of the drive IC and transmits the recovered electric charges to the display panel through a second path of the drive IC when re-driving the display panel, wherein the energy recovering unit includes a first diode having a cathode connected at a first node between the power switch and the drive IC, a first transistor having a second electrode connected to an anode of the first diode, a storage device connected between a first electrode of the first transistor and a prescribed reference voltage, a second diode having its cathode connected to the first electrode of the first transistor, and a second transistor having a second electrode connected to an anode of the second diode and a first electrode connected to the first node between the power switch and the drive IC.
To further achieve the above objects in a whole or in part, there is provided a method of operating a display panel in accordance with the present invention that includes driving a display panel with a first power supply voltage through a drive IC, recovering electric charges charged in a panel capacitor of the display panel through a first path of the drive IC in a energy recovery circuit, transmitting the recovered electric charges to the display panel through a second path of the drive IC, re-driving the display panel with the first power supply through the first path of the drive IC, and repeating the recovering through re-driving steps.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.